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PI6C484321
260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Product Features
* Dual differential 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 53.33MHz to 366.67MHz * Crystal input frequency range: 14MHz to 40MHz * TEST_CLK freqeuncy range: 10MHz to 50MHz * VCO range: 320MHz to 1.1GHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 3ps (typical) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Packages (Pb-free & Green available): - 32-pin LQFP (FB)
Description
The PI6C484321 is a dual output, 3.3V LVPECL Frequency Synthesizer using crystal as the input source. The input source is can be selected from either LVTTL/LVCMOS level input (TEST_CLK pin) or crystal inputs. The VCO operates at a frequency range of 320MHz to 1.1GHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed through a simple 2-wire serial interface or through 11-bit parallel interface. The low phase noise characteristics of the PI6C484321 make it an ideal clock source for Fibre Channel 1 (FC1), Fibre Channel 2 (FC2), 10 Gigabit Fibre Channel (10GFC), Gigabit Ethernet and 10 Gigabit Ethernet (10GbE) applications.
Block Diagram
VCO_SEL
Pin Configuration
VCO_SEL
nP_LOAD
XTAL_SEL TEST_CLK XTAL1 OSC XTAL2
0 1
XTAL1
32 31 30 29 28 27 26 25 M5 M6 M7 M8
0 1
M4
M3
M2
M1
M0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
24 23 22 21 20 19 18 17
XTAL2 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
PLL
PHASE DETECTOR
MR
? /M
VCO
/3 /4 /5 /6
N0
FOUT0 nFOUT0 FOUT1 nFOUT1
N1 nc VEE
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
1
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Functional Description
The following functional description describes operations using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The PI6C484321 features a fully integrated PLL, thus requires no external components for setting the loop bandwidth. A fundamental crystal is the input to the internal oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz reference frequency to the phase detector. The actual VCO range of the PLL is 320MHz to 1.1GHz. The output of the M divider is used by the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some illegal values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable feature that selects the M divider and N output divider supports two modes: parallel and serial modes. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B to program the VCO Frequency Function Table. The output frequency is defined as follows: fOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK S_DATA S_LOAD nP_LOAD
t
T1
S
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
t
S
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
t
S
M, N
t
H
Time
Parallel & Serial Load Operations
2
PS8765A 08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Pin Description
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc VEE TEST VCC FOUT1, nFOUT2 VCCO FOUT0, nFOUT0 Input Input Input unused Power Output Power Output Power Output Type Pullup Pulldown Pulldown M divider input. Data latched on LOW-to-HIGH transition of nP_ LOAD input. LVCMOS / LVTTL interface levels Determines N output divider value as defined in Table 3C Function table. LVCMOS / LVTTL interface levels No connect Negative supply pins Test output. ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels Positive supply pin Differential output for the synthesizer. LVPECL interface levels Output supply pin Differential output for the synthesizer. LVPECL interface levels Active High Master reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shirft register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Control transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels Analog supply pin Pullup Pulldown Selects between crystals or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels Crystal oscillator inputs Pulldown Pullup Parallel load input to determine when data present at M8:M0 is loaded into M divider, and when data is present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Controls the clock synthesizer to be in PLL or bypass mode. LVCMOS /LVTTL interface levels Description
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
Notes 1.
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL1, XTAL2 nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup and Pulldown refer to internal input resistors. See Pin characterstics Table for typical values.
3
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input capacitance Input Pullup resistor Input Pulldown resistor Min. Typ. 4 51 51 Max. Units pF k
Parallel and Serial Modes Function Table
Inputs MR H L L L L L L L
Notes:
nP_LOAD X L H H H H H
M X Data Data X X X X X
N X Data Data X X X X X
S_LOAD X X L L L
S_CLOCK S_DATA X X X L L X X X X Data Data Data X
Conditions Reset mode, forces outputs LOW. Data on M and N input passed directly to the M divider. TEST output forced LOW Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs Serial input mode. Shift register is loaded with data on S-DATA on each rising edge of S_CLOCK Contents of the shift register are passed to the M divider M divider and N output divider values are latched Parallel or serial input do not affect shift registers
H Data S_Data passed directly to M divider as it is clocked L = Low, H = High, X = Don't care, = Rising Edge, and = Falling edge Transition
Programmable VCO Frequency Example Based On 25MHz input
VCO Freq. 625 650 675 775 M Divider 25 26 27 31 256 M8 0 0 0 0 128 M7 0 0 0 0 64 M6 0 0 0 0 32 M5 0 0 0 0 16 M4 1 1 1 1 8 M3 1 1 1 1 4 M2 0 0 0 1 2 M1 0 1 1 1 1 M0 1 0 1 1
Programmable Output Divider FunctionTable
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 3 4 5 6 Output Frequency (MHz) Min. 106.67 80 64 53.33 Max. 366.67 275 220 183.33
Notes: Fout_min = Fvco_min / N = 320MHz / N Fout_max = Fvco_max /N = 1100MHz / N
4
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer Absolute Maximum Ratings
Supply voltage, VCC ............................................................ 4.6V Inputs, VI .................................................... -0.5V to VCC + 0.5V Outputs, VO (LVPECL)............................-0.5V to VDDO + 0.5V Outputs, IO (LVCMOS) Continuous current .......................................................... 50mA Surge current ................................................................. 100mA Package Thermal Impedance, Theta JA ......... 47.9C/W (0 lfpm) Storage Temperature, TSTG ................................-65 C to 150C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may effect product reliability.
Commonly Used Configuration Function Table
Input Crystal (MHz) 19.44 19.53125 25 25 25.50 25.50 25.50 38.88 20 20 M Divider Value 32 32 25 25 25 25 25 16 N Divider Value 4 4 4 5 3 4 6 4 Output Frequency (MHz) 155.52 156.25 156.25 125 212.50 159.375 106.25 155.52 75 83.33
5
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer LVCMOS / LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C to 70C
Symbol VIH Input High Voltage Parameter VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK VIL Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL VOH VOL
Notes 1.
Test Condition
Min. 2 2 -0.3 -0.3
Typ.
Max. VCC +0.3V VCC +0.3V 0.8 1.3 150 5
Units
V
IIH
Input High Current
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 2.6
A
IIL
Input Low Current
Output High Voltage Output Low Voltage
TEST(1) TEST(1)
0.5
V
Outputs terminated with 50 to VCC/2. See Parameters Measurement Information table, 3.3V Output Load Test Circuit Figure.
Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C to 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Positive supply voltage Analog supply voltage Output supply voltage Power supply current Analog supply current Min. 3.135 3.135 3.135 Typ. 3.3 3.3 3.3 Max. 3.465 3.465 3.465 180 30 mA V Units
LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C to 70C
Symbol VOH VOL VSWING
Notes 1.
Parameter Output high Output low voltage(1) voltage(1)
Test Condition
Min. VCCO - 1.4 VCCO -2.0 0.6
Typ.
Max. VCCO -1.0 VCCO -1.7 1.0
Units V
Peak-to-Peak output voltage swing
Outputs terminated with 50 to VCC -2V. See Parameter Measurement Section, 3.3V output load test circuit.
6
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V5%, TA 0C to 70C
Symbol fIN
Notes 1.
Parameter TEST_CLK (1) Input Frequency XTAL, XTAL2(1) S_CLOCK
Test Condition
Min. 14 14
Typ.
Max. 40 40 50
Units MHz
For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate with in the 200MHz to 700MHz range. Using minimum input frequency of 12MHz, valid values of M are 17 M 58. Using the maximun frequency of 25MHz, valid values of M are 8 M 28.
Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series resistance (ESR) Shunt Capacitance 14 Test Condition Min. Typ. Fundamental 40 50 7 MHz pF Max. Units
AC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C to 70C
Symbol FOUT tjit(per) tsk(o) tR tF tS Period jitter, Parameter Output frequency RMS(1, 3) 20% to 80% 20% to 80% 200 200 5 5 5 5 5 5 45 PLL lock time 55 1 % ms ns Output skew(2, 3) Output rise time Output fall time Mx, Nx to nP_LOAD Setup time S_DATA to S_CLOCK S_CLOCK to S_LOAD Mx, Nx to nP_LOAD tH
odc
Test Condition
Min. 103.3
Typ. 3
Max. 260 5 15 700 700
Units MHz ps ps ps
Hold time
S_DATA to S_CLOCK S_CLOCK to S_LOAD
tLOCK
Notes: 1. Jitter performance using XTAL inputs. 2. Defined as skew between outputs with the same supply voltage and with equal load conditions. Measured at the output differential cross points. 3. This parameter is defined in accordance with JEDEC standard 65
7
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Paramater Measurement Information
2V
VCC, VCCA, VCCO
Qx
SCOPE
nFOUTx FOUTx
LVPECL
VEE
nQx
nFOUTy FOUTy
tsk(o)
-1.3V 0.165V
3.3V Output Load Test Circuit
Output Skew
VOH VREF VOL
nFOUTx FOUTx
Pulse Width t
PERIOD
1 2 3 4 6
contains 68.26% of all measurements contains 95.4% of all measurements contains 99.73% of all measurements contains 99.99366% of all measurements contains (100-1.973x10-7)% of all measurements Histogram (First edge after trigger)
odc =
t PW t PERIOD
Reference Point
(Trigger Edge)
Mean Period
Period Jitter
Output Duty Cycle/Pulse Width/Period
80% Clock Outputs 20% tR
80% VSW I N G 20% tF
Output Rise/Fall Time
8
PS8765A
08/01/05
PI6C484321 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Packaging Mechanical: 32-pin LQFP (FB)
9.00 BSC .354 Square
Square
7.00 .276
BSC
0.09 0.20 .004 .008
0.25 mm
GAUGE PLANE
0 7
1.60 Max. .063
.004 0.10
Seating Plane
0.45 .018 0.75 .030
1.00 REF .039
0.30 .012 0.45 .018
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
0.80 BSC .032
0.05 0.15 .002 .006
1.35 1.45 .053 .057
Ordering Information
Ordering Code PI6C484321FB PI6C484321FBE Package Code FB FB 32-Pin LQFP Pb-free & Green, 32-Pin LQFP PackageType
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * http://www.pericom.com
9
PS8765A 08/01/05

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